1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device for programming defective address information during a repair operation, and a method for operating the semiconductor memory device.
2. Description of the Related Art
Methods for repairing defective cells are divided into those that are repair in the wafer stage and those that repair in the package stage. Repair operations performed in the package stage are referred to as Post-Package Repair (PPR) operations.
A semiconductor memory device generally includes a fuse circuit capable of programming an address of a repair target memory cell. Herein, a programming operation indicates a series of operations for storing an address of a repair target memory cell in a fuse circuit. The fuse circuit includes a plurality of fuse sets, and the fuse sets are divided into a fuse set to be used during a PPR mode and a fuse set to be used during a test mode, which is not the PPR mode, i.e., a non-PPR mode.